검색결과 : 14건
| No. | Article |
|---|---|
| 1 |
Study of carrier transport in strained and unstrained SOI tri-gate and omega-gate silicon nanowire MOSFETs Koyama M, Casse M, Coquand R, Barraud S, Vizioz C, Comboroure C, Perreau P, Maffini-Alvaro V, Tabone C, Tosti L, Barnola S, Delaye V, Aussenac F, Ghibaudo G, Iwai H, Reimbold G Solid-State Electronics, 84, 46, 2013 |
| 2 |
Scaling of Trigate nanowire (NW) MOSFETs to sub-7 nm width: to Single Electron Transistor Deshpande V, Barraud S, Jehl X, Wacquez R, Vinet M, Coquand R, Roche B, Voisin B, Triozon F, Vizioz C, Tosti L, Previtali B, Perreau P, Poiroux T, Sanquer M, Faynot O Solid-State Electronics, 84, 179, 2013 |
| 3 |
Impact of local back biasing on performance in hybrid FDSOI/bulk high-k/metal gate low power (LP) technology Fenouillet-Beranger C, Perreau P, Benoist T, Richier C, Haendler S, Pradelle J, Bustos J, Brun P, Tosti L, Weber O, Andrieu F, Orlando B, Pellissier-Tanon D, Abbate F, Richard C, Beneyton R, Gregoire M, Ducote J, Gouraud P, Margain A, Borowiak C, Bianchini R, Planes N, Gourvest E, Bourdelle KK, Nguyen BY, Poiroux T, Skotnicki T, Faynot O, Boeuf F Solid-State Electronics, 88, 15, 2013 |
| 4 |
Scaling of high-kappa/metal-gate TriGate SOI nanowire transistors down to 10 nm width Coquand R, Barraud S, Casse M, Leroux P, Vizioz C, Comboroure C, Perreau P, Ernst E, Samson MP, Maffini-Alvaro V, Tabone C, Barnola S, Munteanu D, Ghibaudo G, Monfray S, Boeuf F, Poiroux T Solid-State Electronics, 88, 32, 2013 |
| 5 |
Transistors on hybrid UTBB/Bulk substrates fabricated by local internal BOX dissolution Nguyen P, Andrieu F, Casse M, Tabone C, Perreau P, Lafond D, Dansas H, Tosti L, Veytizou C, Landru D, Kononchuk O, Guiot E, Nguyen BY, Faynot O, Poiroux T Solid-State Electronics, 90, 39, 2013 |
| 6 |
Study of substrate orientations impact on Ultra Thin Buried Oxide (UTBOX) FDSOI High-K Metal gate technology performances Ben Akkez I, Fenouillet-Beranger C, Cros A, Perreau P, Haendler S, Weber O, Andrieu F, Pellissier-Tanon D, Abbate F, Richard C, Beneyton R, Gouraud P, Margain A, Borowiak C, Gourvest E, Bourdelle KK, Nguyen BY, Poiroux T, Skotnicki T, Faynot O, Balestra F, Ghibaudo G, Boeuf F Solid-State Electronics, 90, 143, 2013 |
| 7 |
Characterization and modeling of capacitances in FD-SOI devices Ben Akkez I, Cros A, Fenouillet-Beranger C, Perreau P, Margain A, Boeuf F, Balestra F, Ghibaudo G Solid-State Electronics, 71, 53, 2012 |
| 8 |
Parasitic bipolar impact in 32 nm undoped channel Ultra-Thin BOX (UTBOX) and biased Ground Plane FDSOI high-k/metal gate technology Fenouillet-Beranger C, Perreau P, Boulenc P, Tosti L, Barnola S, Andrieu F, Weber O, Beneyton R, Perrot C, de Buttet C, Abbate F, Campidelli Y, Pinzelli L, Gouraud P, Margain A, Peru S, Bourdelle KK, Nguyen BY, Boedt F, Poiroux T, Faynot O, Skotnicki T, Boeuf F Solid-State Electronics, 74, 32, 2012 |
| 9 |
Dual strained channel CMOS in FDSOI architecture: New insights on the device performance Le Royer C, Casse M, Cooper D, Andrieu F, Weber O, Brevard L, Perreau P, Damlencourt JF, Baudot S, Previtali B, Tabone C, Allain F, Scheiblin P, Rauer C, Figuet C, Aulnette C, Daval N, Nguyen BY, Bourdelle KK, Gyani J, Valenza M Solid-State Electronics, 65-66, 9, 2011 |
| 10 |
Impact of a 10 nm ultra-thin BOX (UTBOX) and ground plane on FDSOI devices for 32 nm node and below Fenouillet-Beranger C, Perreau P, Denorme S, Tosti L, Andrieu F, Weber O, Monfray S, Barnola S, Arvet C, Campidelli Y, Haendler S, Beneyton R, Perrot C, de Buttet C, Gros P, Pham-Nguyen L, Leverd F, Gouraud P, Abbate F, Baron F, Torres A, Laviron C, Pinzelli L, Vetier J, Borowiak C, Margain A, Delprat D, Boedt F, Bourdelle K, Nguyen BY, Faynot O, Skotnicki T Solid-State Electronics, 54(9), 849, 2010 |