검색결과 : 6건
| No. | Article |
|---|---|
| 1 |
Low temperature influence on performance and transport of Omega-gate p-type SiGe-on-insulator nanowire MOSFETs Paz BC, Casse M, Barraud S, Reimbold G, Vinet M, Faynot O, Pavanello MA Solid-State Electronics, 159, 83, 2019 |
| 2 |
Electrical characterization of vertically stacked p-FET SOI nanowires Paz BC, Casse M, Barraud S, Reimbold G, Vinet M, Faynot O, Pavanello MA Solid-State Electronics, 141, 84, 2018 |
| 3 |
Methodology to separate channel conductions of two level vertically stacked SOI nanowire MOSFETs Paz BC, Casse M, Barraud S, Reimbold G, Vinet M, Faynot O, Pavanello MA Solid-State Electronics, 149, 62, 2018 |
| 4 |
Study of silicon n- and p-FET SOI nanowires concerning analog performance down to 100 K Paz BC, Casse M, Barraud S, Reimbold G, Vinet M, Faynot O, Pavanello MA Solid-State Electronics, 128, 60, 2017 |
| 5 |
Charge-based compact analytical model for triple-gate junctionless nanowire transistors Avila-Herrera F, Paz BC, Cerdeira A, Estrada M, Pavanello MA Solid-State Electronics, 122, 23, 2016 |
| 6 |
Compact model for short-channel symmetric double-gate junctionless transistors Avila-Herrera F, Cerdeira A, Paz BC, Estrada M, Iniguez B, Pavanello MA Solid-State Electronics, 111, 196, 2015 |