화학공학소재연구정보센터
검색결과 : 7건
No. Article
1 Monte-Carlo simulation of MOSFETs with band offsets in the source and drain
Braccioli M, Palestri P, Mouis M, Poiroux T, Vinet M, Le Carval G, Fiegna C, Sangiorgi E, Deleonibus S
Solid-State Electronics, 52(4), 506, 2008
2 105 nm Gate length pMOSFETs with high-K and metal gate fabricated in a Si process line on 200 mm GeOI wafers
Le Royer C, Clavelier L, Tabone C, Romanjek K, Deguet C, Sanchez L, Hartmann JM, Roure MC, Grampeix H, Soliveres S, Le Carval G, Truche R, Pouydebasque A, Vinet M, Deleonibus S
Solid-State Electronics, 52(9), 1285, 2008
3 Experimental determination of the channel backscattering coefficient on 10-70 nm-metal-gate, Double-Gate transistors
Barral V, Poiroux T, Vinet M, Widiez J, Previtali B, Grosgeorges P, Le Carval G, Barraud S, Autran JL, Munteanu D, Deleonibus S
Solid-State Electronics, 51(4), 537, 2007
4 Comparative study of the fabricated and simulated Impact Ionization MOS (IMOS)
Mayer F, Le Royer C, Le Carval G, Tabone C, Claveller L, Deleonibus S
Solid-State Electronics, 51(4), 579, 2007
5 Investigation of nonstationary transport and quantum effects in realistic deep submicrometerr partially depleted SOI technology
Munteanu D, Le Carval G, Fenouillet-Beranger C, Faynot O
Electrochemical and Solid State Letters, 5(5), G29, 2002
6 Assessment of anomalous behavior in hydrodynamic simulation of CMOS bulk and partially depleted SOI devices
Munteanu D, Le Carval G
Journal of the Electrochemical Society, 149(10), G574, 2002
7 Impact of technological parameters on non-stationary transport in realistic 50 nm MOSFET technology
Munteanu D, Le Carval G, Guegan G
Solid-State Electronics, 46(7), 1045, 2002