화학공학소재연구정보센터
검색결과 : 10건
No. Article
1 A Domino 10-Step Total Synthesis of FR252921 and Its Analogues, Complex Macrocyclic Immunosuppressants
Chen Y, Coussanes G, Souris C, Aillard P, Kaldre D, Runggatscher K, Kubicek S, Di Mauro G, Maryasin B, Maulide N
Journal of the American Chemical Society, 141(35), 13772, 2019
2 Improvement in drain-induced-barrier-lowering and on-state current characteristics of bulk Si fin field-effect-transistors using high temperature Phosphorus extension ion implantation
Kikuchi Y, Hopf T, Mannaert G, Everaert JL, Kubicek S, Eyben P, Waite A, Borniquel JID, Variam N, Mocuta D, Horiguchi N
Solid-State Electronics, 152, 58, 2019
3 Properties and growth peculiarities of Si0.30Ge0.70 stressor integrated in 14 nm fin-based p-type metal-oxide-semiconductor field-effect transistors
Hikavyy A, Rosseel E, Kubicek S, Mannaert G, Favia P, Bender H, Loo R, Horiguchi N
Thin Solid Films, 602, 72, 2016
4 Bulk FinFET fabrication with new approaches for oxide topography control using dry removal techniques
Redolfi A, Kubicek S, Rooyackers R, Kim MS, Sleeckx E, Devriendt K, Shamiryan D, Vandeweyer T, Delande T, Horiguchi N, Togo M, Wouters JMD, Jurczak M, Hoffmann T, Cockburn A, Gravey V, Diehl DL
Solid-State Electronics, 71, 106, 2012
5 A Selective Inhibitor and Probe of the Cellular Functions of Jumonji C Domain-Containing Histone Demethylases
Luo XL, Liu YX, Kubicek S, Myllyharju J, Tumber A, Ng S, Che KH, Podoll J, Heightman TD, Oppermann U, Schreiber SL, Wang X
Journal of the American Chemical Society, 133(24), 9451, 2011
6 Benchmarking SOI and bulk FinFET alternatives for PLANAR CMOS scaling succession
Chiarella T, Witters L, Mercha A, Kerner C, Rakowski M, Ortolland C, Ragnarsson LA, Parvais B, De Keersgieter A, Kubicek S, Redolfi A, Vrancken C, Brus S, Lauwers A, Absil P, Biesemans S, Hoffmann T
Solid-State Electronics, 54(9), 855, 2010
7 Superior N- and P-MOSFET scalability using carbon co-implantation and spike annealing
Augendre E, Pawlak BJ, Kubicek S, Hoffmann T, Chiarella T, Kerner C, Severi S, Falepin A, Ramos J, De Keersgieter A, Eyben P, Vanhaeren D, Vandervorst W, Jurczak M, Absil P, Biesemans S
Solid-State Electronics, 51(11-12), 1432, 2007
8 A new technique to fabricate ultra-shallow-junctions, combining in situ vapour HCl etching and in situ doped epitaxial SiGe re-growth
Loo R, Caymax M, Meunier-Beillard P, Peytier I, Holsteyns F, Kubicek S, Verheyen P, Lindsay R, Richard O
Applied Surface Science, 224(1-4), 63, 2004
9 Secondary impact ionization and device aging in deep submicron MOS devices with various transistor architectures
Marchand B, Cretu B, Ghibaudo G, Balestra F, Blachier D, Leroux C, Deleonibus S, Guegan G, Reimbold G, Kubicek S, DeMeyer K
Solid-State Electronics, 46(3), 337, 2002
10 Transistor optimisation for a low cost, high performance 0.13 mu m CMOS technology
Augendre E, Kubicek S, De Keersgieter A, Mertens S, Lindsay R, Verbeeck R, Van Laer J, Dupas L, Badenes G
Solid-State Electronics, 46(7), 959, 2002