검색결과 : 4건
| No. | Article |
|---|---|
| 1 |
Analysis and modeling of wafer-level process variability in 28 nm FD-SOI using split C-V measurements Pradeep K, Poiroux T, Scheer P, Juge A, Gouget G, Ghibaudo G Solid-State Electronics, 145, 19, 2018 |
| 2 |
Obtaining DC and AC isothermal electrical characteristics for RF MOSFET Sahoo AK, Fregonese S, Scheer P, Celi D, Juge A, Zimmer T Solid-State Electronics, 106, 78, 2015 |
| 3 |
Modeling of MOSFET parasitic capacitances, and their impact on circuit performance Mueller J, Thoma R, Demircan E, Bernicot C, Juge A Solid-State Electronics, 51(11-12), 1485, 2007 |
| 4 |
DC and AC MOS transistor modelling in presence of high gate leakage and experimental validation Gilibert F, Rideau D, Bernardini S, Scheer P, Minondo M, Roy D, Gouget G, Juge A Solid-State Electronics, 48(4), 597, 2004 |