검색결과 : 5건
| No. | Article |
|---|---|
| 1 |
Reconfigurable field effect transistor for advanced CMOS: Advantages and limitations Navarro C, Barraud S, Martinie S, Lacord J, Jaud MA, Vinet M Solid-State Electronics, 128, 155, 2017 |
| 2 |
Extra-low parasitic gate-to-contacts capacitance architecture for sub-14 nm transistor nodes Niebojewski H, Le Royer C, Morand Y, Rozeau O, Jaud MA, Dubois E, Poiroux T, Bensahel D Solid-State Electronics, 97, 45, 2014 |
| 3 |
A unified short-channel compact model for cylindrical surrounding-gate MOSFET Cousin B, Reyboz M, Rozeau O, Jaud MA, Ernst T, Jomaah J Solid-State Electronics, 56(1), 40, 2011 |
| 4 |
In-depth physical investigation of GeOI pMOSFET by TCAD calibrated simulation Grandchamp B, Jaud MA, Scheiblin P, Romanjek K, Hutin L, Le Royer C, Vinet M Solid-State Electronics, 57(1), 67, 2011 |
| 5 |
High performance 70 nm gate length germanium-on-insulator pMOSFET with high-k/metal gate Romanjek K, Hutin L, Le Royer C, Pouydebasque A, Jaud MA, Tabone C, Augendre E, Sanchez L, Hartmann JM, Grampeix H, Mazzocchi V, Soliveres S, Truche R, Clavelier L, Scheiblin P, Garros X, Reimbold G, Vinet M, Boulanger F, Deleonibus S Solid-State Electronics, 53(7), 723, 2009 |