검색결과 : 4건
| No. | Article |
|---|---|
| 1 |
Some issues of hot-carrier degradation and negative bias temperature instability of advanced SOICMOS transistors Ioannou DP, Ioannou DE Solid-State Electronics, 51(2), 268, 2007 |
| 2 |
Worst case stress conditions for hot carrier induced degradation of p-channel SOI MOSFETs Ioannou DP, Mishra R, Ioannou DE, Liu ST, Hughes HL Solid-State Electronics, 50(6), 929, 2006 |
| 3 |
Double gate (DG)-SOI ratioed logic with symmetric DG load - a novel approach for sub 50 nm low-voltage/low-power circuit design Mitra S, Salman A, Ioannou DP, Tretz C, Ioannou DE Solid-State Electronics, 48(10-11), 1727, 2004 |
| 4 |
Beta engineering and circuit styles for SEU hardening PD-SOI SRAM cells Ioannou DP, Ioannou DE Solid-State Electronics, 48(10-11), 1947, 2004 |