화학공학소재연구정보센터
검색결과 : 9건
No. Article
1 Self-aligned multi-channel silicon nanowire field-effect transistors
Zhu H, Li QL, Yuan H, Baumgart H, Ioannou DE, Richter CA
Solid-State Electronics, 78, 92, 2012
2 ESD performance of 65 nm partially depleted n and p channel SOI MOSFETs
Mishra R, Ioannou DE, Mitra S, Gauthier R, Seguin C, Halbach R
Solid-State Electronics, 54(4), 357, 2010
3 Design and optimization of the SOI field effect diode (FED) for ESD protection
Yang Y, Salman AA, Ioannou DE, Beebe SG
Solid-State Electronics, 52(10), 1482, 2008
4 Some issues of hot-carrier degradation and negative bias temperature instability of advanced SOICMOS transistors
Ioannou DP, Ioannou DE
Solid-State Electronics, 51(2), 268, 2007
5 Worst case stress conditions for hot carrier induced degradation of p-channel SOI MOSFETs
Ioannou DP, Mishra R, Ioannou DE, Liu ST, Hughes HL
Solid-State Electronics, 50(6), 929, 2006
6 Double gate (DG)-SOI ratioed logic with symmetric DG load - a novel approach for sub 50 nm low-voltage/low-power circuit design
Mitra S, Salman A, Ioannou DP, Tretz C, Ioannou DE
Solid-State Electronics, 48(10-11), 1727, 2004
7 Beta engineering and circuit styles for SEU hardening PD-SOI SRAM cells
Ioannou DP, Ioannou DE
Solid-State Electronics, 48(10-11), 1947, 2004
8 Device physics considerations for SOI domino circuit design
Subba N, Mitra S, Salman A, Ioannou DE
Solid-State Electronics, 47(2), 175, 2003
9 Transient thermal simulations of a three-dimensional unit cell in power control systems and high-power microwave devices
Buot FA, Mittereder JA, Anderson WT, Ioannou DE
Solid-State Electronics, 46(1), 123, 2002