검색결과 : 4건
| No. | Article |
|---|---|
| 1 |
Influence of silicon nanocrystal size and density on the performance of non-volatile memory arrays Rao RA, Gasquet HP, Steimle RF, Rinkenberger G, Straub S, Muralidhar R, Anderson SGH, Yater JA, Ledezma JC, Hamilton J, Acred B, Swift CT, Hradsky B, Peschke J, Sadd M, Prinz EJ, Chang KM, White BE Solid-State Electronics, 49(11), 1722, 2005 |
| 2 |
A model for the channel potential of charge-trapping memories and its implications for device scaling Sadd M, Anderson SGH, Hradsky B, Muralidhar R, Prinz EJ, Rao R, Straub S, Steimle RF, Swift CT, White BE, Yater JA Solid-State Electronics, 49(11), 1754, 2005 |
| 3 |
Silicon nanocrystal based memory devices for NVM and DRAM applications Rao RA, Steimle RF, Sadd M, Swift CT, Hradsky B, Straub S, Merchant T, Stoker M, Anderson SGH, Rossow M, Yater J, Acred B, Harber K, Prinz EJ, White BE, Muralidhar R Solid-State Electronics, 48(9), 1463, 2004 |
| 4 |
HfO2 gate dielectrics deposited via tetrakis diethylamido hafnium Schaeffer J, Edwards NV, Liu R, Roan D, Hradsky B, Gregory R, Kulik J, Duda E, Contreras L, Christiansen J, Zollner S, Tobin P, Nguyen BY, Nieh R, Ramon M, Rao R, Hegde R, Rai R, Baker J, Voight S Journal of the Electrochemical Society, 150(4), F67, 2003 |