검색결과 : 2건
| No. | Article |
|---|---|
| 1 |
Single, double and surround gate vertical MOSFETs with reduced parasitic capacitance Gili E, Kunz VD, de Groot CH, Uchino T, Ashburn P, Donaghy DC, Hall S, Wang Y, Hemment PLF Solid-State Electronics, 48(4), 511, 2004 |
| 2 |
Formation of conducting and insulating layered structures in Si by ion implantation - Process control using FTIR spectroscopy Katsidis CC, Siapkas DI, Robinson AK, Hemment PLF Journal of the Electrochemical Society, 148(12), G704, 2001 |