검색결과 : 3건
| No. | Article |
|---|---|
| 1 |
A comprehensive analysis on scaling prospects of dual-bit channel engineered SONOS NOR-flash EEPROM cells Datta A, Mahapatra S Solid-State Electronics, 54(4), 397, 2010 |
| 2 |
Effects of switching from < 1 1 0 > to < 1 0 0 > channel orientation and tensile stress on n-channel and p-channel metal-oxide-semiconductor transistors Yang PZ, Lau WS, Lai SW, Lo VL, Siah SY, Chan L Solid-State Electronics, 54(4), 461, 2010 |
| 3 |
Selection of gate length and gate bias to make nanoscale metal-oxide-semiconductor transistors less sensitive to both statistical gate length variation and temperature variation Yang PZ, Lau WS, Lai SW, Lo VL, Siah SY, Chan L Solid-State Electronics, 54(11), 1304, 2010 |