검색결과 : 130건
| No. | Article |
|---|---|
| 1 |
Doping profile extraction in thin SOI films: Application to A2RAM Wakam FT, Lacord J, Bawedin M, Martinie S, Cristoloveanu S, Ghibaudo G, Barbe JC Solid-State Electronics, 159, 3, 2019 |
| 2 |
New prospects on high on-current and steep subthreshold slope for innovative Tunnel FET architectures Llorente CD, Colinge JP, Martinie S, Cristoloveanu S, Wan J, Le Royer C, Ghibaudo G, Vinet M Solid-State Electronics, 159, 26, 2019 |
| 3 |
Impact of contact and channel resistance on the frequency-dependent capacitance and conductance of pseudo-MOSFET Sato S, Ghibaudo G, Benea L, Ionica I, Omura Y, Cristoloveanu S Solid-State Electronics, 159, 197, 2019 |
| 4 |
Determination of well flat band condition in thin film FDSOI transistors using C-V measurement for accurate parameter extraction Mohamad B, Leroux C, Reimbold G, Ghibaudo G Solid-State Electronics, 139, 88, 2018 |
| 5 |
New insights on SOI Tunnel FETs with low-temperature process flow for CoolCube (TM) integration Llorente CD, Le Royer C, Batude P, Fenouillet-Beranger C, Martinie S, Lu CMV, Allain F, Colinge JP, Cristoloveanu S, Ghibaudo G, Vinet M Solid-State Electronics, 144, 78, 2018 |
| 6 |
Static and low frequency noise characterization of ultra-thin body InAs MOSFETs Karatsori TA, Pastorek M, Theodorou CG, Fadjie A, Wichmann N, Desplanque L, Wallart X, Bollaert S, Dimitriadis CA, Ghibaudo G Solid-State Electronics, 143, 56, 2018 |
| 7 |
Electrical characteristics of silicon percolating nanonet-based field effect transistors in the presence of dispersion Cazimajou T, Legallais M, Mouis M, Ternon C, Salem B, Ghibaudo G Solid-State Electronics, 143, 83, 2018 |
| 8 |
Compact modeling of nanoscale triple-gate junctionless transistors covering drift-diffusion to quasi-ballistic carrier transport Oproglidis TA, Karatsori TA, Barraud S, Ghibaudo G, Dimitriadis CA Solid-State Electronics, 142, 25, 2018 |
| 9 |
Series resistance in different operation regime of junctionless transistors Jeon DY, Park SJ, Mouis M, Barraud S, Kim GT, Ghibaudo G Solid-State Electronics, 141, 92, 2018 |
| 10 |
Analysis and modeling of wafer-level process variability in 28 nm FD-SOI using split C-V measurements Pradeep K, Poiroux T, Scheer P, Juge A, Gouget G, Ghibaudo G Solid-State Electronics, 145, 19, 2018 |