검색결과 : 11건
| No. | Article |
|---|---|
| 1 |
FDSOI bottom MOSFETs stability versus top transistor thermal budget featuring 3D monolithic integration Fenouillet-Beranger C, Previtali B, Batude P, Nemouchi F, Casse M, Garros X, Tosti L, Rambal N, Lafond D, Dansas H, Pasini L, Brunet L, Deprat F, Gregoire M, Mellier M, Vinet M Solid-State Electronics, 113, 2, 2015 |
| 2 |
Superior performance and Hot Carrier reliability of strained FDSOI nMOSFETs for advanced CMOS technology nodes Besnard G, Garros X, Andrieu F, Nguyen P, Van den Daele W, Reynaud P, Schwarzenbach W, Delprat D, Bourdelle KK, Reimbold G, Cristoloveanu S Solid-State Electronics, 113, 127, 2015 |
| 3 |
Reliability of ultra-thin buried oxides for multi-V-T FDSOI technology Besnard G, Garros X, Nguyen P, Andrieu F, Reynaud P, Van Den Daele W, Bourdelle KK, Schwarzenbach W, Toffoli A, Kies R, Delprat D, Reimbold G, Cristoloveanu S Solid-State Electronics, 97, 8, 2014 |
| 4 |
A study of N-induced traps due to a nitrided gate in high-kappa/metal gate nMOSFETs and their impact on electron mobility Casse M, Garros X, Weber O, Andrieu F, Reimbold G, Boulanger F Solid-State Electronics, 65-66, 139, 2011 |
| 5 |
High performance 70 nm gate length germanium-on-insulator pMOSFET with high-k/metal gate Romanjek K, Hutin L, Le Royer C, Pouydebasque A, Jaud MA, Tabone C, Augendre E, Sanchez L, Hartmann JM, Grampeix H, Mazzocchi V, Soliveres S, Truche R, Clavelier L, Scheiblin P, Garros X, Reimbold G, Vinet M, Boulanger F, Deleonibus S Solid-State Electronics, 53(7), 723, 2009 |
| 6 |
FDSOI devices with thin BOX and ground plane integration for 32 nm node and below Fenouillet-Beranger C, Denorme S, Perreau P, Buj C, Faynot O, Andrieu F, Tosti L, Barnola S, Salvetat T, Garros X, Casse M, Allain F, Loubet N, Pham-Nguyen L, Deloffre E, Gros-Jean M, Beneyton R, Laviron C, Marin M, Leyris C, Haendler S, Leverd F, Gouraud P, Scheiblin P, Clement L, Pantel R, Deleonibus S, Skotnicki T Solid-State Electronics, 53(7), 730, 2009 |
| 7 |
Impact of a HTO/Al2O3 bi-layer blocking oxide in nitride-trap non-volatile memories Bocquet M, Molas G, Perniola L, Garros X, Buckley J, Gely M, Colonna JP, Grampeix H, Martin F, Vidal V, Toffoli A, Deleonibus S, Ghibaudo G, Pananakakis G, De Salvo B Solid-State Electronics, 53(7), 786, 2009 |
| 8 |
Impact of the gate stack on the electrical performances of 3D multi-channel MOSFET (MCFET) on SOI Bernard E, Ernst T, Guillaumot B, Vulliet N, Garros X, Maffini-Alvaro V, Coronel P, Skotnicki T, Deleonibus S Solid-State Electronics, 52(9), 1297, 2008 |
| 9 |
Investigation of hafnium-aluminate alloys in view of integration as interpoly dielectrics of future Flash memories Molas G, Bocquet M, Buckley J, Grampeix H, Gely M, Colonna JP, Licitra C, Rochat N, Veyront T, Garros X, Martin F, Brianceau P, Vidal V, Bongiorno C, Lombardo S, De Salvo B, Deleonibus S Solid-State Electronics, 51(11-12), 1540, 2007 |
| 10 |
Electrical and physico-chemical characterization of HfO2/SiO2 gate oxide stacks prepared by atomic layer deposition Damlencourt JF, Renault O, Samour D, Papon AM, Leroux C, Martin F, Marthon S, Semeria MN, Garros X Solid-State Electronics, 47(10), 1613, 2003 |