검색결과 : 3건
| No. | Article |
|---|---|
| 1 |
Suppression of gate-induced drain leakage by optimization of junction profiles in 22 nm and 32 nm SOI nFETs Schenk A Solid-State Electronics, 54(2), 115, 2010 |
| 2 |
Multi-Subband Monte Carlo study of device orientation effects in ultra-short channel DGSOI Sampedro C, Gamiz F, Godoy A, Valin R, Garcia-Loureiro A, Ruiz FG Solid-State Electronics, 54(2), 131, 2010 |
| 3 |
Parameter sensitivity for optimal design of 65 nm node double gate SOI transistors Lim TC, Armstrong GA Solid-State Electronics, 49(6), 1034, 2005 |