검색결과 : 4건
| No. | Article |
|---|---|
| 1 |
Managing annealing pattern effects in 45 nm low power CMOS technology Morin P, Cacho F, Beneyton R, Dumont B, Colin A, Bono H, Villaret A, Josse E, Bianchini R Solid-State Electronics, 54(9), 897, 2010 |
| 2 |
Dual metal gate FinFET integration by Ta/Mo diffusion technology for V-t reduction and multi-V-t CMOS application Matsukawa T, Endo K, Liu YX, O'uchi S, Ishikawa Y, Yamauchi H, Tsukada J, Ishii K, Sakamoto K, Suzuki E, Masahara M Solid-State Electronics, 53(7), 701, 2009 |
| 3 |
A robust 45 nm gate-length CMOSFET for 90 nm Hi-speed technology Lim KY, Chan V, Rengarajan R, Lee HK, Rovedo N, Lim EH, Yang S, Jamin F, Nguyen P, Lin W, Lai CW, Teh YW, Lee J, Kim L, Luo Z, Ng H, Sudijono J, Wann C, Yang I Solid-State Electronics, 50(4), 579, 2006 |
| 4 |
Integration issues of high-k and metal gate into conventional CMOS technology Song SC, Zhang Z, Huffman C, Bae SH, Sim JH, Kirsch P, Majhi P, Moumen N, Lee BH Thin Solid Films, 504(1-2), 170, 2006 |