검색결과 : 10건
| No. | Article |
|---|---|
| 1 |
Optimized design of Si-cap layer in strained-SiGe channel p-MOSFETs based on computational and experimental approaches Sato-Iwanaga J, Inoue A, Sorada H, Takagi T, Rothschild A, Loo R, Biesemans S, Ito C, Liu Y, Dutton RW, Tsuchiya H Solid-State Electronics, 91, 1, 2014 |
| 2 |
Benchmarking SOI and bulk FinFET alternatives for PLANAR CMOS scaling succession Chiarella T, Witters L, Mercha A, Kerner C, Rakowski M, Ortolland C, Ragnarsson LA, Parvais B, De Keersgieter A, Kubicek S, Redolfi A, Vrancken C, Brus S, Lauwers A, Absil P, Biesemans S, Hoffmann T Solid-State Electronics, 54(9), 855, 2010 |
| 3 |
Sub-threshold study of undoped trigate nFinFET Tettamanzi GC, Lansbergen GP, Paul A, Lee S, Deosarran PA, Collaert N, Klimeck G, Biesemans S, Rogge S Thin Solid Films, 518(9), 2521, 2010 |
| 4 |
Multi-gate devices for the 32 nm technology node and beyond Collaert N, De Keersgieter A, Dixit A, Ferain I, Lai LS, Lenoble D, Mercha A, Nackaerts A, Pawlak BJ, Rooyackers R, Schulz T, San KT, Son NJ, Van Dal MJH, Verheyen P, von Arnim K, Witters L, Meyer KD, Biesemans S, Jurczak M Solid-State Electronics, 52(9), 1291, 2008 |
| 5 |
Achieving low-V-T Ni-FUSICMOS via lanthanide incorporation in the gate stack Veloso A, Yu HY, Lauwers A, Chang SZ, Adelmann C, Onsia B, Demand M, Brus S, Vrancken C, Singanamalla R, Lehnen P, Kittl J, Kauerauf T, Vos R, O'Sullivan BJ, Van Elshocht S, Mitsuhashi R, Whittemore G, Yin KM, Niwa M, Hoffmann T, Absil P, Jurczak M, Biesemans S Solid-State Electronics, 52(9), 1303, 2008 |
| 6 |
Multi-gate devices for the 32 nm technology node and beyond: Challenges for Selective Epitaxial Growth Collaert N, Rooyackers R, Hikavyy A, Dixit A, Leys F, Verheyen P, Loo R, Jurczak M, Biesemans S Thin Solid Films, 517(1), 101, 2008 |
| 7 |
Superior N- and P-MOSFET scalability using carbon co-implantation and spike annealing Augendre E, Pawlak BJ, Kubicek S, Hoffmann T, Chiarella T, Kerner C, Severi S, Falepin A, Ramos J, De Keersgieter A, Eyben P, Vanhaeren D, Vandervorst W, Jurczak M, Absil P, Biesemans S Solid-State Electronics, 51(11-12), 1432, 2007 |
| 8 |
Minimization of specific contact resistance in multiple gate NFETs by selective epitaxial growth of Si in the HDD regions Dixit A, Anil KG, Rooyackers R, Leys F, Kaiser M, Collaert N, De Meyer K, Jurczak M, Biesemans S Solid-State Electronics, 50(4), 587, 2006 |
| 9 |
L-eff extraction for sub-100 nm MOSFET devices Ye QY, Biesemans S Solid-State Electronics, 48(1), 163, 2004 |
| 10 |
Papers from the Sixth International Workshop on Fabrication, Characterization, and Modeling of Ultra-Shallow Doping Profiles in Semiconductors - 22-26 April 2001 Napa Valley, California -Preface Ukraintsev V, Biesemans S, Majeed F, Miller D, Mulligan A Journal of Vacuum Science & Technology B, 20(1), 406, 2002 |