검색결과 : 5건
| No. | Article |
|---|---|
| 1 |
Study of silicon n- and p-FET SOI nanowires concerning analog performance down to 100 K Paz BC, Casse M, Barraud S, Reimbold G, Vinet M, Faynot O, Pavanello MA Solid-State Electronics, 128, 60, 2017 |
| 2 |
Experimental demonstration of strained Si nanowire GAA n-TFETs and inverter operation with complementary TFET logic at low supply voltages Luong GV, Strangio S, Tiedemannn A, Lenk S, Trellenkamp S, Bourdelle KK, Zhao QT, Mantl S Solid-State Electronics, 115, 152, 2016 |
| 3 |
Analog performance of vertical nanowire TFETs as a function of temperature and transport mechanism Martino MD, Neves F, Agopian PGD, Martino JA, Vandooren A, Rooyackers R, Simoen E, Thean A, Claeys C Solid-State Electronics, 112, 51, 2015 |
| 4 |
Behavior of triple-gate Bulk FinFETs with and without DTMOS operation de Andrade MGC, Martino JA, Aoulaiche M, Collaert N, Simoen E, Claeys C Solid-State Electronics, 71, 63, 2012 |
| 5 |
The low-frequency noise behaviour of graded-channel SOI nMOSFETs Simoen E, Claeys C, Chung TM, Flandre D, Pavanello MA, Martino JA, Raskin JP Solid-State Electronics, 51(2), 260, 2007 |