검색결과 : 4건
| No. | Article |
|---|---|
| 1 |
Leakage characterization of top select transistor for program disturbance optimization in 3D NAND flash Zhang Y, Jin L, Jiang DD, Zou XQ, Zhao ZG, Gao J, Zeng M, Zhou WB, Tang ZY, Huo ZL Solid-State Electronics, 141, 18, 2018 |
| 2 |
Vertical-Channel STacked ARray (VCSTAR) for 3D NAND flash memory Park SH, Kim Y, Kim W, Seo JY, Park BG Solid-State Electronics, 78, 34, 2012 |
| 3 |
3D NAND flash memory with laterally-recessed channel (LRC) and connection gate architecture Yun JG, Lee JD, Park BG Solid-State Electronics, 55(1), 37, 2011 |
| 4 |
Stacked-nanowire device with virtual source/drain (SD-VSD) for 3D NAND flash memory application Yun JG, Cho S, Park BG Solid-State Electronics, 64(1), 42, 2011 |